`timescale 1ns/10ps
`define clock_period 20

module non_blocking_tb;

	wire outb;
	wire outc;
	reg clk_50M;
	reg ina;

	non_blocking nb0(
		.Clk_50M(clk_50M),
		.Ina(ina),
		.Outb(outb),
		.Outc(outc)
	);
	
	always #(`clock_period / 2) clk_50M = ~clk_50M;
	
	initial begin
		//时钟初始化
		clk_50M = 1'b0;
		ina = 1'b1;
		
		#(`clock_period * 2);
		
		ina = 1'b0;
		#(`clock_period * 2);
		
		ina = 1'b1;
		
		#(`clock_period * 2);
		
		ina = 1'b0;
		#(`clock_period * 2);
		
		$stop;
	end

endmodule
